When a microcomputer constructed by adding a CPU with ROM, RAM and other peripheral functions is applied to various user applications, usually, it is necessary to change the hardware of the microcomputer in connection with functions required for each application, and thus there is a problem that the number of variations of products is increased.
Therefore, there may be considered such a construction that an operation as a function is implemented by software. For example, JP-A-6-250857 discloses a microcomputer in which two tasks (A, L) are subjected to time-divisional parallel processing in one CPU and execution of a branch instruction is prohibited in the L-task to establish fix-looping, whereby the value of a program counter is used as a timer or runaway monitoring processing of the A-task is executed.
However, in order to implement an “input capture” function of achieving a timer value in accordance with a level variation of a specific input terminal or a more complicated peripheral function such as serial communication or the like in the microcomputer disclosed in the above publication, the program size is greatly increased.
Furthermore, JP-A-2004-38521 discloses a construction in which a prefix instruction is disposed just before a target instruction described in a program and the function of the target instruction is extended in accordance with the state of a flag set in the prefix instruction.
However, in the technique disclosed in JP-A-2004-38521, it is necessary to insert the prefix instruction in order to extend the instruction function, and thus the program size is necessarily increased.
It is generally required that more kinds of instructions are installed in the CPU, and in order to satisfy this requirement, it is necessary to compress the size of the overall instruction code to a maximum. Japanese Patent No. 2,682,469 discloses one of these techniques. As shown in FIG. 20, this technique is an encoding system of code-expanding an offset operand (lower-order bits (2 to 0) of offset) as an operation code field for the same operation code (ope2) to thereby allocate plural instructions.
That is, the technique disclosed in the above Japanese Patent is established on the basis of the assumption that “0” is allocated to the lower-order bits of the offset field which will serve as bits for code expansion. Accordingly, this technique is not applicable to an instruction code in which other parameters are set to the lower-order bits.